The invention relates to static timing analysis, STA, in particular to graph-based static timing analysis, GBA.
Current integrated circuit, IC, designs, may include an extremely large number, for example in the order of 107-108 or even more, of cells such as logic gates and synchronous or sequential devices connected by interconnects. The synchronous or sequential devices include flip-flops and latches. Herein, a register denotes a synchronous or sequential device comprising at least one flip-flop or latch.
In such synchronous designs, violations of timing constraints may occur. Such violations may include setup time violations and hold time violations. A setup time violation occurs when a signal arrives too late at a register, while a hold time violation occurs when an input signal changes too soon after an active transition of a corresponding clock signal. The arrival time of a signal is subject to variations of several sources including variations in temperature, voltage, manufacturing processes and so forth.
By means of STA, for example in the course of electronic design automation, EDA, it is achieved to verify that the timing constraints are met despite said variations to ensure proper operation of the IC.
In contrast to path-based STA, where individual timing paths are analyzed in isolation, in GBA a multitude of timing paths is analyzed simultaneously. A delay value is associated to each cell and each interconnect of the design to evaluate a delay of the timing paths of the design. To account for variations such as on-chip variations due to manufacturing variability, a global derating factor may be applied for the delay values of all cells and interconnects across the whole chip. However, such global derating factor results in a too pessimistic estimation for the derated delay in particular with the increasing influence of on-chip variations.
Advanced on-chip variation, AOCV, analysis is an STA methodology whereby the derating factor of a cell or an interconnect in a timing path is taken to be a function of the path depth, that is the number of logic stages in the path, and a physical distance covered by the path. Both depth and distance are measured from the common point of a timing path, defined as the output pin of the last cell in the portion of the clock path common to launch and capture segments of the timing path.
However, due to its path-base nature, presently known AOCV analysis introduces a large amount of pessimism, that is underestimated path slack values, into GBA due to exaggerated derating factors. This pessimism originates for example from the following two sources:
i) signals launched at a register are associated with the common point resulting in the most conservative, that is worst-case, among the common points of all timing paths launched by that register, and
ii) the AOCV metrics, that is logic depth and distance, applied at a given timing arc are dictated by the worst-case metrics for all timing paths which traverse that timing arc. In the following, pessimism associated with i) is denoted common point pessimism, while the pessimism associated with ii) is denoted merging pessimism.
Any amount of extra pessimism in STA is harmful as it has a direct effect on both the development and verification effort and the performance and power profiles of the final product.